1. Field of the Invention
The present invention relates to a D/A converter (digital/analog converter) circuit (DAC). In particular, the present invention relates to a DAC used in a driver circuit of a semiconductor device. Further, the present invention relates to a semiconductor device using the DAC.
2. Description of the Related Art
Research and development of thin film transistors (TFTs) using polycrystalline silicon films formed on glass substrates as active layers has been advancing briskly in recent years. A TFT using a polycrystalline silicon film has a mobility which is two orders of magnitude or more higher than the mobility of a TFT that uses an amorphous silicon film, and therefore the electric current value necessary for circuit operation can be sufficiently maintained even if the gate width of the TFT becomes small and highly defined. Accordingly, it is possible to realize a xe2x80x9csystem on panelxe2x80x9d in which a pixel portion of a matrix type flat panel display and a driver circuit are integrally formed on the same substrate.
Cost reductions are made possible with the xe2x80x9csystem on panelxe2x80x9d because the number of fabricating steps and inspection steps of the display can be reduced. Further, it is possible to make the flat panel display smaller in size and with more high definition.
An issue relating to advances in making flat panel displays even smaller and higher definition is the realization of a DAC capable of high speed operation and occupying only a small amount of surface area on a substrate.
Several types of DACs exist, and capacitance divided types and resistance divided types can be given as typical. Compared to resistance divided DACs, capacitance divided DACs is capable of high speed operation with a relatively small surface area.
Shown in FIG. 11 is an example of a conventional capacitance divided DAC. The conventional capacitance divided DAC shown in FIG. 11 has n switches SW[1] to SW[n] controlled by each bit D1 to Dn of an n-bit digital signal, and n capacitors C, 2C, . . . , 2nxe2x88x921C, connected to each switch, and a reset switch SWR. Further, an electric power source A (electric potential VA) and an electric power source B (electric potential VB) are connected to this conventional DAC. The electric power source A and the electric power source B are maintained at different electric potentials. Furthermore, the electric potential VOUT of an analog signal output from the DAC is imparted to an output line.
Corresponding bits of a digital signal are input to the switches SW[1] to SW[n], respectively. Selection of whether each of the capacitors is connected to the electric power source A or to the electric power source B is then made in accordance with information indicating 0 or 1 contained in the input digital signal.
Operation of the conventional DAC is explained in order. The conventional DAC can be explained by dividing it into reset periods TR and write in periods TA.
First, the reset switch SWR is closed during a reset period TR. Further, all of the switches SW[1] to SW[n] are connected to the same electric power source in accordance with a digital signal. It is assumed that they are connected to the electric power source A here. An equivalent circuit diagram of the conventional DAC immediately prior to the end of the reset period is shown in FIG. 12A. Note that reference symbol CA denotes the combined capacitance of all the capacitors.
A write in period TA begins after the reset period TR is complete, and each bit of the digital signal, which has the arbitrary 0 or 1 information, controls the switches SW[1] to SW[n]. Electric charges are then supplied to the n capacitors by each capacitor connecting to the electric power source A or the electric power source B in accordance with information in each bit. This then becomes a normal state. An equivalent circuit diagram for this point is shown in FIG. 12B. Note that the reference symbol CT denotes the combined capacitance of all the capacitors connected to the electric power source A, and that the reference symbol CB denotes the combined capacitance of the capacitors connected to the electric power source B.
By repeating the reset period TR and the write in period TA stated above, it is possible to convert the digital signal in to an analog signal.
As stated above, the capacitance divided DAC is capable of high speed operation with a relatively smaller surface area compared to a resistance divided DAC, and thus it is considered preferable in making flat panel displays smaller. However, if the number of bits of the digital signal is increased in order to make the flat panel display higher definition, it becomes difficult to suppress the amount of surface area occupied on the substrate, even with capacitance divided DACs.
If each capacitor of a capacitance divided DAC is designed with reduced size in order to reduce the occupied surface area, then the capacitor surface area corresponding to the lowest bit and its capacitance value become smaller. A small shift in the capacitance value develops due to causes such as shifts in the position of masks used during formation of the capacitor, patterning, and unforeseen parasitic capacitance. Therefore, if the capacitors are designed smaller, the ratio of shift in the capacitance value of the capacitor corresponding to the lowest bit becomes large, and it becomes difficult to form a capacitance divided DAC having good linearity.
Further, if the number of corresponding digital signal bits is increased with a resistance divided DAC, then not only does it become difficult to reduce the surface area, but the output resistance also becomes high, and high speed operation becomes difficult.
In view of the above stated problems, an object of the present invention is to manufacture a DAC capable of having a limited surface area, even if the number of digital signal bits is increased in order to a flat panel display further smaller in size of and have high definition, and which also has good linearity at high speed operation.
The applicants of the present invention considered using a resistance divided DAC or a selector circuit as a substitute for capacitors corresponding to the lower bits, which affect the inconsistent linearity of a capacitance divided DAC.
With the present invention, for example, one capacitor corresponding to the lower m bits of an n-bit digital signals D1 to Dn (m less than n), and nxe2x88x92m capacitors corresponding to the upper nxe2x88x92m bits, are formed in a DAC corresponding to the n-bit digital signal. The one capacitor corresponding to the lower m bits of the digital signal is hereafter referred to as a lower bit correspondence capacitor (CL), and the nxe2x88x92m capacitors corresponding to the upper nxe2x88x92m bits are hereafter referred to as upper bit correspondence capacitors (CU).
The capacitance value of the lower bit correspondence capacitor is denoted by C (where C is a constant), and the capacitance values of the nxe2x88x92m upper bit correspondence capacitors are denoted by, in order from the lowest of the upper bits, CU[1]=C, CU[2]=2C, CU[3]=22C, . . . , CU[nxe2x88x92mxe2x88x921]=2nxe2x88x92mxe2x88x922C, and CU[nxe2x88x92m]=2nxe2x88x92mxe2x88x921C.
The DAC of the present invention is connected to an electric power source A (electric potential VA) and to an electric power source B (electric potential VB) having different electric potentials. Electrical charging of the nxe2x88x92m upper bit correspondence capacitors by the two electric power sources is controlled by each bit of the upper nxe2x88x92m bits of the digital signal.
Further, the lower m bits of the digital signal are converted into analog in the resistance divided DAC, or selector circuit, corresponding to the lower m bits in the DAC of the present invention, and input to a lower bit output line as an analog signal corresponding to the lower bits (electric potential VL). The lower bit correspondence capacitor is charged in accordance with the analog signal corresponding to the lower bits which is input to the lower bit output line.
The capacitors of the DAC of the present invention are all connected to one output line, and the electric potential of the output lines, namely the electric potential of the analog signal, is determined by the electric charge supplied to each capacitor in accordance with the information of 1 or 0 in each bit of the digital signal.
In accordance with the above structure, a DAC capable of handling a digital signal having a high number of bits without losing linearity can be formed, while maintaining advantages as the capacitance divided type, such as the ability to suppress the relative amount of surface area while operating at high speed, an advantage of capacitance division.
Structures of the present invention will be described below.
According to the present invention, there is provided a D/A converter circuit for converting n-bits digital signals (where n is a natural number) to analog signals, characterized in that:
the D/A converter circuit has nxe2x88x92m+1 capacitors (where m is a natural number less than n);
electrical charging of one capacitor from among the nxe2x88x92m+1 capacitors is controlled by the lower m bits, from among the n bits, of the digital signals; and electrical charging of the remaining nxe2x88x92m capacitors from among the nxe2x88x92m+1 capacitors is controlled by the upper nxe2x88x92m bits, from among the n bits, of the digital signals.
According to the present invention, there is provided a D/A converter circuit for converting n-bits digital signals (where n is a natural number) to analog signals, characterized in that:
the D/A converter circuit has nxe2x88x92m+1 capacitors (where m is a natural number less than n);
electrical charging of one capacitor, having a capacitance value of C (where C is a constant), from among the nxe2x88x92m+1 capacitors is controlled by the lower m bits, from among the n bits, of the digital signals;
electrical charging of the remaining nxe2x88x92m capacitors from among the nxe2x88x92m+1 capacitors is controlled by the upper nxe2x88x92m bits, from among the n bits of the digital signals; and
the remaining nxe2x88x92m capacitors have capacitance values expressed by C, 2C, 22C, . . . , 2nxe2x88x92mxe2x88x921C, respectively.
According to the present invention, there is provided a D/A converter circuit for converting n-bits digital signals (where n is a natural number) to analog signals, characterized in that:
the D/A converter circuit has nxe2x88x92m+1 capacitors (where m is a natural number less than n), and 2m resistors;
electric charges determined by the lower m bits of the digital signals, from among the n bits, and by the 2m resistors are supplied to one capacitor from among the nxe2x88x92m+1 capacitors; and
electric charges determined by the upper nxe2x88x92m bits of the digital signals, from among the n bits are supplied to the remaining nxe2x88x92m capacitors from among the nxe2x88x92m+1 capacitors.
According to the present invention, there is provided a D/A converter circuit for converting n-bits digital signals (where n is a natural number) to analog signals, characterized in that:
the D/A converter circuit has nxe2x88x92m+1 capacitors (where m is a natural number less than n), and 2m resistors;
electric charges determined by the lower m bits of the digital signals, from among the n bits, and by the 2m resistors are supplied to one capacitor from among the nxe2x88x92m+1 capacitors;
the resistance values of all of the 2m resistors are the same; and
electric charges determined by the upper nxe2x88x92m bits of the digital signals, from among the n bits are supplied to the remaining nxe2x88x92m capacitors from among the nxe2x88x92m+1 capacitors.
According to the present invention, there is provided a D/A converter circuit for converting n-bits digital signals (where n is a natural number) to analog signals, characterized in that:
the D/A converter circuit has nxe2x88x92m+1 capacitors (where m is a natural number less than n), and 2m gradation voltage lines;
one of the 2m gradation voltage lines is selected by the lower m bits of the digital signals, from among the n bits, and electric charge is supplied to one capacitor having a capacitance value of C (where C is a constant), from among the nxe2x88x92m+1 capacitors, by the electric potential of the selected gradation voltage line;
electric charging of the remaining nxe2x88x92m capacitors, from among the nxe2x88x92m+1 capacitors, is controlled by the upper nxe2x88x92m bits of the digital signals, from among the n bit digital signal; and
the remaining nxe2x88x92m capacitors have capacitance values expressed by C, 2C, 22C, . . . , 2nxe2x88x92mxe2x88x921C, respectively.
The present invention may have a feature such that the 2m resistors are connected in series.
The present invention may have a feature such that the two resistors, from among the 2m resistors, which have one terminal not connected to another resistor, are connected to a low voltage side electric power source, and to a high voltage side electric power source, respectively.
The present invention may have a feature such that the amount of electric charge supplied to the nxe2x88x92m+1 capacitors in a reset period is always maintained at a specific value.
The present invention may have a feature such that a semiconductor device includes the D/A converter circuit which is employed.
The present invention may have a feature such that the present invention is applied to: a display device; a digital still camera; a notebook personal computer; a mobile computer; a DVD player; a head mounted display; a video camera; or a portable telephone.